The present invention relates to network protocol processing generally and, more particularly, to a Transmission Control Protocol/Internet Protocol stack processing in silicon.
Firmware-based Transmission Control Protocol (TCP)/Internet Protocol (IP) processors fabricated using existing technology have achieved processing speeds for network data of 100 megabits per second (Mbps). Application specific network processor circuits have achieved processing speeds of 1 gigabit per second (Gbps). Advancements in the Ethernet bus and similar buses require data rate processing speeds of at least 10 Gbps.
The application specific network processor circuits operating on byte-wide data streams must be clocked at 125 megahertz (MHz) to achieve the 1 Gbps processing rate. Scaling the application specific network processor circuits to 10 Gbps requires increasing the clock to 1.25 gigahertz (GHz). Current large-scale production technology cannot economically produce application specific network processor circuits that operate at the 1.25 GHz clock rate.
The present invention concerns a circuit for converting data between communication protocols at different levels of a protocol stack. The circuit generally comprises a first processor and a second processor. The first processor may be configured to convert the data between a first communication protocol and a second communication protocol. The first processor may have a plurality of first rows each having at least one first block each configured to process a portion of the data. At least one of the first rows may have a plurality of the first blocks. The second processor may be configured to convert the data between the second communication protocol and a third communication protocol. The second processor may have a plurality of second rows each having at least one second block each configured to process a portion of the data. At least one of the second rows may have a plurality of the second blocks.
The objects, features and advantages of the present invention include providing a high speed protocol stack processing circuit that may (i) process high network data rates, (ii) operate at existing clock rates, (iii) reduced hardware/silicon requirements, (iv) reduce bus loading, and/or (v) perform parallel operations.